This invention relates to semiconductor devices, and more particularly to a method of forming electro-static discharge protection devices in a manner compatible with a self-aligned silicided CMOS process for making integrated circuits.
Electrostatic discharge (ESD) can cause failure of an MOS integrated circuit device by overheating various components due to overcurrent, or due to breakdown of thin oxide, or due to other mechanisms. The output buffers or other I/O nodes of an MOS integrated circuit can be self protecting against ESD failures. During an ESD event, the injected current causes the N-channel MOS pull-down transistor of the output driver to enter snap-back, a low resistance regime that can conduct large amounts of current. But the use of silicided source/drain areas and silicided gates in MOSFET's, particularly LDD (lightly-doped drain) MOSFETs have had a deleterious effect on the self-protection tendency in MOS integrated circuits. Further, it has been shown that for very thin dielectrics, output nodes may be self-protecting from catastrophic damage, but may be weakened by ESD so that their current drive capability is more quickly reduced over time, so that long-term reliability is decreased.
In particular, self-aligned silicided areas pose a problem in MOS integrated circuits because the conducting contact (the silicide) to the reverse-biased junction (the drain of the MOS transistor in snap-back) is very close to the junction edge, which is the source of heat when an ESD event occurs. This causes the silicide to melt, or agglomerate, causing a failure. Another reason why silicides can reduce reliability is that the source/drain series resistance is severely reduced, meaning that there is less of a "ballasting" effect, and current during an ESD event is more easily able to collapse into a thin filament, leading to more heating and early failure.
Nevertheless, siliciding, which reduces resistance, is required for output driver transistors for performance reasons in many circuits. Attempts to minimize the deleterious effects of silicide on the ESD devices in such circuits by layout and deivce design have not been entirely successful, nor have they generally been applicable to many circuit configurations. These attempts have not addressed the problem of reduction in long term reliability associated with thin dielectrics. One such attempt employed the well junctions for the source and drain regions of the protection device using the field oxide for the gate dielectric, which moves the silicide away from the edge of the deep well junction, but such a device is difficult to trigger into snapback, and its snapback voltage may be larger than that of the pull-down device, so that it does not protect it. Accordingly, a requirement is that the protection device still have the necessary electrical characteristics to perform its function as needed.